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 Carrier board AMBPEX5

Digital signal processing module AMBPEX5 is designed for building high-performance systems of collecting data and digital signal processing on the base of PC with PCI Express bus. Module contains ADM interface, in which submodules of ADM family are installed. Module is used in systems with direct data transmission to PC or with digital signal processing in programmable logical circuit (FPGA).

Module has units with PCI Express x8 interface, ADM interface, buffer pools (DDR2 SDRAM up to 512Őű64. and CIO SBSRAM up to 2x2Mx32), submodule control unit and reference frequency synthesis. Module environment flexibility is determined by submodule control options, dataflow and digital processing on FPGA of Virtex 5 family. FPGA with capacity from 5000 up to 11000 gates may be installed depending on the task.

Module is used cooperatively with ADM family submodules. ADM submodules have part of the system with physical layer of digital interface, analog-digital converters and digital-analog converters with satellite adapter circuit, controlling, filtering and synchronization circuits.

Channels extension and productivity extension are achieved through cooperative operation (synchronized or independent) of several devices.

Standard software kit for AMBPEX5 includes program for complex analysis of ISVI signals with functions of oscillograph and spectrograph for signal written in file.

For developing own applied programs using DAQ Tools is recommended. DAQ Tools is a tool for developing applied software for AMBPEX5 modules.

Tools allow to setup moduleís parameters and perform data input/output both in RAM and HDD. Software kit includes system driver, set of dynamic libraries, programmerís manual and program examples for C++.

 


Module's exterior:


Key features:

  • FPGA FPGA Virtex 5 XC5VLX110T/VSX50T/VSX95T/VFX70T
  • Interface PCI Express x8 , data transfer speed up to 1500 MB/s
  • Interface PCI Express x4 , data transfer speed up to 700 MB/s
  • Support of analog-digital ADM submodules
  • Dynamic memory:  SODIMM DDR2 up to 4096 MB
  • Static memory: CIO SBSRAM up to 16 MB
  • Inner module synchronization by quartz generators, by outer TTL/CMOS/ECL signals
  • Programmable transformation frequencies
  • PLL-based frequency synthesizer up to 1000 MHz
  • Start/stop of input/output process: software-based; from outer TTL, CMOS, ECL signals; threshold; pre-trigger mode
  • Universal 16-bit digital input/output port LVTTL/LVDS
  • Capability of joint synchronized or independent work of several modules
  • Possibility of installing 2 SFP+ modules
  • With installed submodule occupies one slot in PC

Structural sheme:

Structure AMBPEX5

 

System bus PCIExpress on FPGA Virtex 5 

ADM interface used here is described at ADM interface page. All main units and sockets of interface are displayed in the scheme.

Digital port is made at PIOX connector and is dedicated to input/output of digital signal in LVCMOS/LVDS standard.

Inner frequency generator. One of three generators is installed: standard LVCMOS generator up to 100 MHz. PECL generator up to 200 MHz. Precise TXCO generator

Frequency synthesizer including AD9956 chip works for frequencies up to 1000 MHz. Synthesized frequency output to DAX connector is supported.

Starting synchronization unit feeds clock frequency from SDX connector and allows drawing up star/stop events from outer devices.

Intermodule synchronization uses SYNX connector for its work. This socket is used for providing synchronized data registration. Clock frequency, data registration and data readiness transfer between modules is supported.

 

InSys Micro Inc., New York

E-mail: Sales@InSys-USA.com